Exploring VLSI Domains: Preparation Strategies and Job Market Insights
The Department of ECE conducted a webinar on ‘Exploring VLSI Domains: Preparation Strategies and Job Market Insights’ on 22nd March 2025 for 3rd year ECE students. Resource persons for the webinar were Mr. Chyavan Phadke, SoC Design Engineer, Intel Corporation, Vancouver, Canada (SDMIT Alumnus) and Mr. Karthik Bharadwaj, ASIC Verification Engineer, Microchip Technology, USA (SDMIT Alumnus).The webinar provided comprehensive insights into the ASIC design flow, elaborated on the pivotal role of a verification engineer, highlighted the essential skill sets required to excel in this domain, and explored the various subdomains within VLSI design and verification. Mr. Niranjan Mamadapur, Asst. Professor and Dr. Madhusudhana K, Associate Professor & HOD, ECE Dept. coordinated the event.
