Alumni Interaction: Job opportunities in VLSI domain
The Department of ECE conducted a webinar on ‘Job opportunities in VLSI domain’ on
19th September 2024 for final year ECE students. Resource persons for the webinar were
Mr. Karthik Bharadwaj (Alumnus SDMIT) ASIC Verification Engineer, Microchip Technology, USA and Mr. Chyavan Phadke (Alumnus SDMIT) SoC Design Engineer, Intel Corporation, USA. During the session steps involved in ASIC design flow, Role of a verification engineer, Skill set needed to become verification engineer, different subdomains of VLSI were the topics discussed in the webinar. Mr. Niranjan Mamadapur, Asst. Professor, ECE Dept coordinated the event.
